搜索资源列表
vmm-1.1c
- VMM(Verification Methodology Manual) Kit (Ver1.1C) for Mentor s Questa and Incisive Software
i2s_vmm
- inter IC Sound design with test bench written in Verification Methodology Manual.
VerificationMethodologyManualforSystemVerilog
- Verification Methodology Manual for SystemVerilog
vmm
- verification methodology manual 英文原版和 论文《基于VMM的芯片验证平台设计》-verification methodology manual for systemverilog
uvm_users_guide_1.2
- uvm验证方法学用户参考手册或指导，非常有用，对IC验证工程师来说，UVM方法学是非常重要的- 46/5000 Uvm yànzhèng fāngfǎ xué yònghù cānkǎo shǒucè huò zhǐdǎo, fēicháng yǒuyòng, duì IC yànzhèng gōngchéngshī lái shuō,UVM fāngfǎ xué shì fēicháng zhòngyào de Uvm Validation Methodology User Ref
高级验证方法学(AVM)中文版
- AVM（高级验证方法学）验证手册，是用SystemVerilog和SystemC两种语言实现的。(AVM (Advanced Verification Methodology) verification manual is implemented in system Verilog and system C.)